Akida 1.0 Hardware constraints
Warning
The following constraints concern only Akida 1.0 IP based solutions and the AKD1000 reference SoC.
For compatibility with multiple possible hardware backends downstream, CNN2SNN and the Akida simulator impose few constraints on layer dimensions. However, hardware does have limits in this respect, which will be checked at the stage of mapping a model to a specific device (real or virtual). This page details the limits for the AKD1000 SoC.
Please refer to Akida V1 layers for layers description.
Input dimensions
Width |
Height |
Channels |
[5:256] |
>= 5 |
1, 3 |
Convolution parameters
Kernel Size |
Stride |
Type |
3×3, 5×5, 7×7 |
1, 2, 3 |
Same, Valid |
Maximum number of filters
Kernel Sise |
3×3 |
5×5 |
7×7 |
Max(1 ch) |
512 |
192 |
96 |
Max(3 ch) |
192 |
64 |
32 |
Max Pooling size
1×1, 1×2, 2×1, 2×2
Quantization bitwidth
Input |
Weights |
Activation |
8 |
1, 2, 4, 8 |
1, 2, 4 |
Convolution parameters
Kernel Size |
Stride |
Type |
1×1, 3×3, 5×5, 7×7 |
1, 2 |
Same |
Max Pooling parameters
Size |
Stride |
1×1, 2×2 |
1, 2 |
Global Average Pooling width
[1:32]
Quantization bitwidth
Input |
Weights |
Activation |
1, 2, 4 |
1, 2, 4 |
1, 2, 4 |
Convolution parameters
Kernel Size |
Stride |
Type |
3×3, 5×5, 7×7 |
1, 2 |
Same |
Max Pooling parameters
Size |
Stride |
1×1, 2×2 |
1, 2 |
Global Average Pooling width
[1:32]
Quantization bitwidth
Input |
Weights |
Activation |
1, 2, 4 |
2, 4 |
1, 2, 4 |
Input dimensions
Width |
Height |
WxHxC |
1 |
1 |
<= 57334 |
Quantization bitwidth
Input |
Weights |
Activation |
1, 2, 4 |
1, 2, 4 |
1, 2, 4 |